Information stored in a dynamic memory will be irretrievable if not periodically refreshed within a data retention time. Especially in low-power applications, it is desirable to limit the time allocated for and the power consumed during memory refreshing.
As one example of a dynamic memory, consider a dynamic random access memory (DRAM) wherein information is stored as the charge on a cell capacitor. Refreshing such a memory is necessary because the stored charge dissipates, for example, through a leakage resistance across the capacitor. The conventional DRAM includes an array of many thousands of cells arranged for refreshing a row at a time. To refresh the stored charge in each cell, a row of cells is coupled to a row of sense amplifiers until the sense amplifiers reach one of two stable states. Then, the sense amplifier outputs are coupled to the row of cells to recharge each cell to the charge level corresponding to the information originally stored therein.
Selection of rows, sense amplification, and the recharging of cells consume power in inverse proportion to a refresh cycle time. The shorter the refresh cycle time, the more power is consumed. In the conventional DRAM, refreshing is accomplished in cycles. Each row refresh cycle has a period including an active time sufficient for refreshing a row of cells plus an inactive time for other memory operations such as system level reading and writing. Power for refreshing is primarily consumed during the active time. The duration of an aggregate refresh cycle also has a period, herein called the "refresh cycle time," including an active time sufficient for refreshing all rows plus an inactive time. The refresh cycle time must match the row refresh cycle time, though the refresh cycle has considerably less inactive time than the row refresh cycle. In either cycle, it is desirable to increase the inactive time to conserve power and to increase the availability of the memory for system level operations.
Since periodic refreshing of all cells in the DRAM must be accomplished within the data retention time of each cell, the refresh cycle time must be less than the data retention time of the cell having the fastest discharge characteristics. Conventional refresh timing circuits are designed with a refresh cycle time that accommodates a worst case (minimum) data retention time. The worst case time accounts for several effects including variation in geometric tolerances and material concentrations from cell to cell and variations with bias and operating voltages.
Use of conventional refresh timing wastes power in two ways. First, use of worst case cell discharge parameters dictates application of refresh power to the average cell for a time longer than is necessary to recharge the cell, thus extending the active portion of the row refresh cycle. Second, use of the worst case data retention time dictates refreshing prior to the time when refreshing is necessary, i.e. more often than necessary. Consequently, refreshing can more frequently interrupt use of the memory for system level reading and writing, degrading system performance.
In view of these and related problems known in the art, there remains a need for conserving power in systems having dynamic memory and increasing system use of dynamic memory by increasing refresh cycle time, and especially increasing the inactive portion of refresh cycle time.